BIOS Setup

Boot & POST
Above 1 MB Memory Test
BIOS Update
Boot From LAN First
Boot Sequence
X Boot Sequence EXT Means
Boot Up Floppy Seek

Boot Up Numlock Status
Boot Up System Speed
Boot Virus Detection
CPUID Instruction
Cyrix 6x86 / MII CPU ID
Daylight Saving
Delay IDE Initial
Deturbo Mode
Drive B
Flash BIOS Protection

Floppy 3 Mode
Halt On
HDD Sequence SCSI/IDE First
Keyboard
LAN Remote Boot
Language Support
Memory Test
Memory Test Tick Sound
Numeric Processor Test
Option ROM Scan

Overclock Warning Message
Quick Power On Self Test
RTC Y2K H/W Roll Over
Scan User Flash Area
Setup Prompt
Small Logo (EPA) Show
Summary Screen
Support Removable Disks under BIOS as Fixed Disks
Swap Floppy Drive
USB Keyboard Support Via

USB Mouse Support Via
Video
Virus Check Reminder
Virus Warning
Wait for F1> If Any Error
Weitek Coprocessor
Beeps
Errors

BIOS Setup

Auto Configuration
Chipset I/O Wait States
Chipset Special Features
Command per Cycle

Delayed Read Request Expiration
Extended I/O Decode
Fast Decode Enable
Host Bus Fast Data Ready
ICH Decode Select
PIIX4 SERR#
Pipelined Function
System Performance
Bit I/O Recovery Time
Bit I/O Recovery Time

Bit ISA I/O Command WS
Bit ISA Mem Command WS
AT Cycle Wait State
Back to Back I/O Delay
Bus Request when FIFO is
Byte Merge Support
CPU Dynamic-Fast-Cycle
CPU Read PCI Retry
CPU-to-PCI 6 DW FIFO
CPU-to-PCI Bridge Retry

CPU to PCI Burst Memory Write
CPU-to-PCI FIFO Cleaning
CPU-to-PCI IDE Posting
CPU to PCI POST/BURST
CPU-to-PCI Read Buffer
CPU to PCI Read Burst
CPU-to-PCI Write Buffer
CPU-to-PCI Write Latency
CPU-to-PCI Write Posting
Delayed Transaction

DRAM-to-PCI 24 DW FIFO
DRAM to PCI RSLP
Early PCI Bus Request
Extra AT Cycle WS
Fast AT Cycle
Fast Back-to-Back
Fast Frame Generation
I/O Posted Write Buffer
I/O Recovery Time
L2 to PCI Read Buffer

Max PCI Burst Size
Passive Release
PCI1 to PCI0 Access
PCI#2 Access #1 Retry
PCI Pipeline
PCI Post-Write Fast
PCI-to-CPU Write Buffer
PCI to CPU Write Pending
PCI-To-CPU Write Posting
PCI-to-DRAM 24 DW FIFO

PCI to DRAM Buffer
PCI-to-DRAM Bursting
PCI-to-DRAM FIFO Cleaning
PCI-to-DRAM Pipeline
PCI-to-DRAM Posting
PCI-to-DRAM Prefetch
PCI to ISA Write Buffer
PCI-to-L2 Checkpoint
PCI-to-L2 Read Wait States
PCI to L2 Write Buffer

PCI-to-L2 Write Wait States
PCI-to-PCI Posting
ROM Wait States
USB Passive Release
Write Post During I/O Bridge Access
Drive NA before BRDY
Extended CPU-PIIX4 PHLDA#
Gate A20 Option

Graphic Posted Write Buff
IBC DEVSEL# Decoding
LOCK Function
NA Delay
NA# Enable
NA# On Single Write Cycle
Negate LOCK#
Single ALE Enable
Stop CPU when PCI Flush
Backoff Processor

Base I/O Address
Branch Target Buffer
CPU ADS# Delay 1T or Not
CPU BIST Enable
CPU Drive Strength
CPU Fast String
CPU Line Read Multiple
CPU Read Multiple Prefetch
I/O Space Access
Processor Number Feature

CPU Speed
CPU Host Clock Select
CPU Ratio
CPU Speed
CPU Vcore
SEL 100/66# Signal
Speed Error Hold
Turbo Frequency
Turbo Mode (75 MHz)
Memory Current

ECC, Parity
CPU Level 2 Cache ECC Check
Data Integrity (PAR/ECC)
DRAM Data Integrity Mode
DRAM ECC/PARITY Select
Memory Parity/ECC Check
Single Bit Error Report

BIOS Setup

Затенение" памяти, выделенная память

Adaptor ROM Shadow C800,16K
Adaptor ROM Shadow CC00,16K
Adaptor ROM Shadow D000,16K
Adaptor ROM Shadow D400,16K
Adaptor ROM Shadow E000,16K
Adaptor ROM Shadow EC00,16K
DC000-DFFFF Shadow
DC00,16K Shadow
Base Memory Address
BIOS Devnode for Shadow RAM

CD Hole
E0000 ROM belongs to ATBUS
E8000 32K Accessible
Extended ROM RAM Area
ISA LFB Size
X ISA LFB Base Address
ISA Mem Block Size
ISA Shared Memory Size
X ISA Shared Memory Base Address
Memory Hole At 15M-16M

Memory Remapping
Memory Reservation
Shadowing Address Ranges (xxxxx-xxxxx Shadow)
System BIOS Shadow
VGA Type
Video BIOS Shadowing
Кэширование памяти
Ext BIOS EC00-EFFF

Cache Extended Memory Area
Cache C800-CBFF
Cache DRAM Memory Area
DC00 - DFFF
KB to 1MB Cacheability
Async L2 Cache Leadoff
Cache Burst Read Cycle
Cache Rd+CPU Wt Pipeline
Cache Timing
CPU External Cache

CPU Internal Cache
Иллюстрация 1
External Cache Write Policy
Internal Cache WB or WT
L2 Cache Allocation
L2 Cache Banks
X 2-Bank L2 Cache Speed,
L2 Cache Burst Addressing
L2 Cache Cacheable Size
L2 Cache Size

L2 Cache Timing
L2 Cacheing Control
Memory above 16MB Cacheable
Non-Cacheable Block-1 Size
Non-Cacheable Block-1 Base
Non-Cacheable Block-2 Base
Block 1 Size
PCI Cycle Cache Hit WS
PCI Master Read Caching
Pipeline

Pipeline Cache Timing
Shadow Memory Cacheable
DC00,16K Shadow
SRAM Back-to-Back
SRAM Type
Sustained 3T Write
SYNC SRAM Support
System BIOS Cacheable
Tag Compare Wait States
Tag Option

Tag Ram Includes Dirty
Tag/Dirty Implement
X Dirty pin selection
USWC Write Posting
Video BIOS Cacheable
Video Memory Cache Mode
Иллюстрация 2
Video RAM Cacheable
Weak Write Ordering

BIOS Setup

Регенерация памяти
Burst Refresh
CAS Before RAS Refresh
CAS-to-RAS Refresh Delay
Concurrent Refresh
Decoupled Refresh
Distributed Refresh
DRAM Ahead Refresh
X DRAM Ahead Refresh Timing

DRAM Burst at 4 Refresh
DRAM CAS# Precharge
DRAM RAS Only Refresh
DRAM RAS# Precharge Time
DRAM Refresh Method
DRAM Refresh Period
DRAM Refresh Queue
DRAM Refresh Queue Depth
Extended Refresh
Fast DRAM Refresh

Hidden Refresh
Hi-Speed Refresh
ISA Refresh
ISA Refresh Period
ISA Refresh Type
PCI-to-DRAM RAS# Precharge
RAS Precharge @Access End
RAS Timeout
Ref/Act Command Delay
Refresh During PCI Cycles

Refresh RAS# Assertion
Refresh Value
Refresh When CPU Hold
SDRAM Idle Limit
SDRAM Precharge Control
SDRAM Refresh
Self-Refresh
Slow Refresh (1:4)
Staggered Refresh
Auto Configuration
Bank nn DRAM Type
Bank nn Numer of Banks
Base Memory Size
CAS# Latency
CAS# Pulse Width
CPU to DRAM Page Mode
DDR_1T/2T_Item
DRAM Clock

DRAM Interleave Mode
DRAM Page Idle Timer
DRAM Prefetch Buffer
DRAM Prefetch Buffer Size
DRAM Prefetch Delay
DRAM Speculative Leadoff
DRAM Speed Selection
DRAM Type
EMS
EMS Memory Base Address

EMS Page Reg I/O Base
EMS Page(n) Addr Extension
Fast MA to RAS# Delay
MA Wait State
OS Select for DRAM >Mb
RAMW# Timing
RAS# Pulse Width
RAS# to CAS# Delay
Read-Around-Write
Read Prefetch Memory RD

SDRAM (CAS Lat/RAS-to-CAS)
SDRAM Configuration
SDRAM Precharge Control

BIOS Setup

Арбитраж, Bus-Master
Arbitration Priority
CPU Priority
DMA/ISA Master Before PCI
Master Priority Rotation

PCI Bus Arbitration
PCI Arbiter Mode
Arbiter Priority on HB1
Bus Mastering
CPU Mstr DEVSEL# Time-out
CPU Mstr Fast Interface
CPU Mstr Post-WR Buffer
CPU Mstr Post-WR Burst Mode
Enable Master
Master Prefetch And Posting

Master Retry Timer
PCI Bus Parking
PCI Master 0 WS Write
PCI Master Access to ISA
PCI master accesses shadow RAM
PCI Master Write Ping-Pong
PCI Master Read Prefetch
PCI Mstr Burst Mode
PCI Mstr DEVSEL# Time-out
PCI Mstr Fast Interface

PCI Mstr Post-WR Buffer
Preempt PCI Master Option
Shared PCI Master Assignment
State Machines
Stop CPU at PCI Master
Все о PCI-шине
PCI 2.1 Support
PCI Clock Frequency
PCI Dynamic Decoding
PCI Latency Timer (PCI Clocks)

PCI Parity Check
PCI Preempt Timer
Peer Concurrency
SERR#
ISA Bus Clock
ISA Slave Wait States
AGP
Init AGP Display First

Joystick Function
LAN Controller
Multiple Monitor Support
Onboard FDC Controller
Onboard Parallel Port
Onboard PCI IDE Enable
Onboard Serial Port 1/2
Иллюстрация 1
OffBoard PCI IDE Card
X OffBoard PCI IDE Secondary IRQ

Secondary Slave ARMD Emulated as
PS/2 Mouse Function Control
USB Controller
USB Keyboard Support
X USB KB/Mouse Legacy Support
X Port 64/60 Emulation
Функции конфигурирования распределения ресурсов
Configuration Mode
X PnP OS
Lock Setup Configuration

Reset Configuration Data
Resources Controlled By
X DMA-n assigned to,
X Memory Resources,
X Reserved Memory Lenght,

BIOS Setup

IRQ
IRQ n Assigned to
IRQ n Used By ISA

IRQ to PCI VGA
Modem Use IRQ
PCI Device Search Order
PCI IRQ Activated by
PCI/PNP ISA IRQ Resource Exclusion
PCI Slot n IRQ Priority
Report No FDD For WIN 95
Slot n IRQ for VGA
Trigger Method
USB IRQ

Use IRQ12 For Mouse Port
DMA
DMA Clock
DMA Line Buffer Mode
DMA n Assigned to
DMA n Used By ISA
DMA Wait States
Extended DMA Registers

PCI/PNP ISA DMA Resource Exclusion
TypeF DMA Buffer Control1(2)
Ports
AC'97 Audio
Audio Controller
X Base I/O address
X MPU I/O address
X Interrupt
X 8-bit DMA channel
X 16-bit DMA channel

Midiport
X Base I/O Address
X Interrupt
Audio Output
Клавиатура и флоппики
KBC Input Clock
Keyboard Reset Control
Typematic Rate Setting
X Typematic Rate (Chars/Sec)
X Typematic Rate Delay (msec)

Floppy Disk Access Control (R/W)

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